* Fixed drive state transition processing of CD block.
* Fixed timer processing of SCSP.
* Fixed resampling processing of SCSP.
* Fixed DMA end interruption processing of SCU.
* Fixed drawing processing of the surface of revolution of VDP2.
* Version of the state saving data changed.
* Main loop processing from the master SH2 center was modified on the system clock center.
* Attendant upon that, SH2 Instruction of option Numbers was modified in 1Block Clock.
* Perhaps somewhat it has become heavy.
* In addition, HSynch Real Clock option was abolished.
* Compiling option was modified from Ver0.09 alpha, but
* That it seems that trouble occurs with cause…
Because you reset on the basis of option, being repaired, perhaps the software where trouble comes out of alpha the [ru].