Changelog for Micro64

======================================================================= bero ===
Version: 1.00.2011.10.20 Build 608 SVN revision: 868
Date: 20. October 2011 Time: 02:41
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- Fixed GeoRAM/NeoRAM emulation
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======================================================================= bero ===
Version: 1.00.2011.10.20 Build 607 SVN revision: 865
Date: 20. October 2011 Time: 02:03
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- Fixed broken cartridge support
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======================================================================= bero ===
Version: 1.00.2011.10.20 Build 606 SVN revision: 863
Date: 20. October 2011 Time: 01:20
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- Added GeoRAM/NeoRAM emulation
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======================================================================= bero ===
Version: 1.00.2011.10.19 Build 605 SVN revision: 857
Date: 19. October 2011 Time: 23:14
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- Added cycle-exact REU emulation and removed the old buggy non-cycle-exact immediate REU emulation
- Fixed a SoftRESET bug
- Fixed a small bug in the BASIC tokenizer in the internal 6502/6510 macro assembler (Keyword "new" had a typo in the keyword string array)
- Added BRK #imm as 2-byte instruction to internal 6502/6510 macro assembler as a optional alternative BRK encoding to addition to the BRK 1-byte immediate instruction
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======================================================================= bero ===
Version: 1.00.2011.10.19 Build 604 SVN revision: 834
Date: 19. October 2011 Time: 02:47
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- Reorangized and optimized IRQ/NMI/RESET/BRK CPU cycle states path, so that a RESET will execute 6 injected-BRK.cycles in real now.
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======================================================================= bero ===
Version: 1.00.2011.10.18 Build 603 SVN revision: 830
Date: 18. October 2011 Time: 19:52
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- Combined IRQ/NMI/RESET/BRK cycle states to a single BRK cycle state path, together with the on-real-6502/6510-IR-register-inject-BRK-on-interrupt-behaviour
- Adjusted SEI and CLI instructions for correct behaviour, when RDY is low (for example for correct IRQ DMA behaviour)
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======================================================================= bero ===
Version: 1.00.2011.10.18 Build 602 SVN revision: 826
Date: 18. October 2011 Time: 02:47
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- Added virtual time-warp additional 3 seconds delay at fast loading
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======================================================================= bero ===
Version: 1.00.2011.10.18 Build 601 SVN revision: 823
Date: 18. October 2011 Time: 02:09
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- Fixed a small bug in PRG RAM injectiop
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======================================================================= bero ===
Version: 1.00.2011.10.18 Build 600 SVN revision: 821
Date: 18. October 2011 Time: 01:51
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- Added PRG/POO/C64 load mode menu (normal over a temporary disk or fast over RAM injection), because it seems that not all PRG/POO/C64 are fast-loadable.
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======================================================================= bero ===
Version: 1.00.2011.10.17 Build 599 SVN revision: 817
Date: 17. October 2011 Time: 20:30
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- Added easyflash cartridge support (readonly for this first time)
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======================================================================= bero ===
Version: 1.00.2011.10.17 Build 598 SVN revision: 807
Date: 17. October 2011 Time: 17:33
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- Fixed code typo bugs in the CPU emulation from the last build 597
- Micro-optimized the CPU emulation a bit
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======================================================================= bero ===
Version: 1.00.2011.10.16 Build 597 SVN revision: 801
Date: 16. October 2011 Time: 21:47
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- Added missing interrupt delay counter stop behaviour when RDY0 if low in the CPU emulation. Fixes the IRQDMA issue.
- Added switch-level transistor-based 6502/6210 CPU simulation (for debugging of the 6502/6510 CPU emulation). It uses the netlists from Visual6502.org in a converted format, but i´ve optimized these for myself for a bit more simulation performance, so that it runs on my Intel i7 2630QM CPU at about 7-8kHz. It´s on-switchable for the main C64 CPU with the "+cpusim" command line parameter.
- Finetuned IRQ/NMI behaviour at tricky IRQ/NMI/BRK cases of the CPU emulation to match the the CPU simulation. But so far, the most other CPU 6502/6510 emulation implementations do handle these cases probably not correct. And I did not mean the BRKNMI, LostBRK, etc. stuff, but I do mean how a real 6502/6510 CPU realizes/manages the B flag st transistor gate logic level in connection to the D1x1 and IRQ/NMI lines and so on, and that IRQ/NMI are just a by-the-in-CPU-PLA injected BRK opcode. So my advice to the other emulator authors: Take the Visual6502.org stuff to your heart, and look at it and use it to debug your CPU emulation. It´s better than all logic analyzer stuff in the most cases in my opinion, because you can look on transistor gate lecel inside the CPU, while it´s working.
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