r153
[+] Added dummy ports 176670 and 176672 on CPU bus. [+] Byte writing in IDE ports (now worked WDBOOT by Oleg H.).
Today (13 hours ago)
alexey.kisly
[Get email change notifications about comments on this revision.] r152
[*] Some progress on IDE emulation: minor fixes.
Yesterday (27 hours ago)
nzeemin
[Get email change notifications about comments on this revision.] r151
[*] Some progress on IDE emulation: minor fixes.
Yesterday (38 hours ago)
nzeemin
[Get email change notifications about comments on this revision.] r150
[*] Some progress on IDE emulation: minor fixes.
Mar 08 (2 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r149
[*] Some progress on IDE emulation: command 20h next sector, command 91h.
Mar 08 (2 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r148
[*] Some progress on IDE emulation: command 20h and other fixes.
Mar 08 (2 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r147
[*] Some progress on IDE emulation.
Mar 07 (3 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r146
[*] Some progress on IDE emulation: read geometry from first sector.
Mar 07 (3 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r145
[*] Some progress on IDE emulation: calculate geometry.
Mar 07 (3 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r144
[*] Some progress on IDE emulation: port mapping etc.
Mar 07 (3 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r143
[*] Some progress on IDE emulation: port mapping etc.
Mar 07 (3 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r142
[*] Preparing for IDE emulation: UI, classes.
Mar 06 (4 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r141
[+] IDE controller ROM images.
Mar 05 (6 days ago)
nzeemin
[Get email change notifications about comments on this revision.] r140
[+] Vlad Zhigalov´s book pages.
Feb 28, 2010
nzeemin
[Get email change notifications about comments on this revision.] r139
[*] Reworked methods SetPortWord,SetPortByte for CPU memory controller [*] Read from memory at DST address for MOVB,CLRB,MFPS commands
Jan 24, 2010
alexey.kisly
[Get email change notifications about comments on this revision.] r138
[+] Processing DCLO and INIT for port 177716 [*] Reworked methods GetPortByte, GetPortWord, SetPortWord, SetPortByte [*] Fixed error when reading an odd address
Jan 17, 2010
alexey.kisly
[Get email change notifications about comments on this revision.] r137
[*] Rewritten work with signals HALT,ACLO,DCLO.
Jan 16, 2010
alexey.kisly
[Get email change notifications about comments on this revision.] r136
Edited wiki page through web user interface.
Jan 09, 2010
nzeemin
[Get email change notifications about comments on this revision.] r135
[*] Fixed bug with reset of emulated computer [*] Fixed bug with reading vector interrupt from memory (firstly must be read new value of vector, then install new values of PC and PSW)
Jan 06, 2010
alexey.kisly
[Get email change notifications about comments on this revision.] r134
[*] Changed interrupt processing and command execution: abort command and interrupt on bus error(TRAP4), CPC and CPSW now working correctly. [+] Implemented double bus error (ДВОЙНОЕ ЗАВИСАНИЕ). [*] Other minor fixes.
Jan 06, 2010
alexey.kisly
[Get email change notifications about comments on this revision.] r133
[*] Removed unused methods from Processor [*] New methods - CommandExecution and InterruptProcessing [*] Reworked methods Execute and DebugTicks
Jan 04, 2010
alexey.kisly